As known in the art, a double-gate transistor structure effectively doubles the electrical current that can be sent through a given transistor. The latest structures are particularly fabricated by means of a thin vertical Silicon (Si) process thus revealing a so-called “FIN Field Effect Transistor” (FinFET) design that relies upon a thin vertical silicon “fin” to help control leakage of current through the transistor when it is in the “off” state (FIG. 1A). This new design approach allows for the creation of new chips with enhanced performance and ever-shrinking feature sizes and geometries. Therefore the mentioned superior leakage control characteristics make FinFET transistors an attractive candidate for future nano-scale CMOS generations since the FinFET process pushes gate lengths below 50 nm.
More particularly, the mentioned CMOS FinFETs are generated through a conventional process or the process steps described in more detail hereinafter (so-called “Sidewall Image Transfer” (SIT) process). When materials are deposited by chemical vapour deposition (CVD) or sputtering processes they typically cover topography in a conformal manner. This means that the vertical thickness of the material deposited at the edge of a step approaches the thickness of the material deposited in flat regions, plus the height of the step. As a consequence, when flat field areas are cleared during dry etching, non-etched material will remain at the edge of the steps in form of a spacer. This sidewall spacer, the width of which is the thickness of the deposited layer in the field regions, can only be removed through additional etching. But instead of etching away the sidewall spacer, the material that formed the step (mandrel) can be selectively etched leaving behind a free-standing spacer, the width of which is the thickness of the original deposited material. In other words, only the combination of surface topography and dry etching inevitably leads to the formation of said sidewall spacers.
The mentioned SIT process is illustrated in more detail referring to FIGS. 1B-1D, each relating to one process step. The shown SIT process is applied to a silicon substrate 105 that comprises an oxide layer 115 on the bottom. Left-hand shown are three plan views showing a mandrel structure 100 out of which a fin loop 120 is generated which represents an active area for the later FinFET. During an intermediate process step, the structure comprises a spacer 110. For a better understanding of the spatial geometry of the structures 100-120, the three process steps (FIGS. 1B-1D) are illustrated right-hand by means of cross-sectional views. As can be seen particularly right-hand in FIG. 1D, as a result of the three process steps, the silicon 105 is being etched using the intermediate spacer 110 as an etching mask resulting in fins 120. This approach has been already used in the fabrication of CMOS FinFETs, so called because the free-standing active silicon spacers resemble fins.
In addition, the designing of these planar CMOS structures involves some design rules. In particular, there exist certain design rules for the design and fabrication of the mentioned fin-based transistor structures. These design rules can be violated in different ways what is illustrated in more detail making reference to FIGS. 2A and 2B.
An important design rule is related to the proximity effect between nearby and essentially parallel arranged fin structures. It is noteworthy that proximity between two fin structures can also be established only in a higher level of design hierarchy where additional regions are linked together, but not in the corresponding sub-level of the underlying circuit design hierarchy.
The mentioned design rules are now described in more detail referring to FIGS. 2A and 2B. The exemplary structural design may consist of two gates ‘Gate 1’ and ‘Gate 2’ 200, 210. The two dotted lines 220 and 230 depict the boundaries of the two gate areas 200, 210. The two gate areas 200, 210, before being assembled, in the present design level, can be understood as adjacent regions of the overall design. After being assembled, the two areas 200, 210 can be understood as contiguous regions. The resulting fin shapes 240 that overlap the two gate areas 200, 210 comprise step-like shapes 260, 270 in the intermediate or overlapping area between the two gate areas 200, 210. The step-like shapes 260, 270 result from an according shift (in vertical direction) between the two gate areas 200, 210 before their assembling. The two gate areas 200, 201, from a functional point of view, define a resulting active area 250 of the underlying FinFET.
In the middle of FIG. 2A, it is schematically illustrated how the resulting fin shapes 240′ are after lithography and subsequent processing. The above mentioned step-like transitions 260, 270 are now deteriorated into inclined lines 260′, 270′. The consequence of this behaviour is illustrated in more detail by way of the enlarged view at the bottom of FIG. 2A of the circular area 280. The deviation from a straight line within the gate area 210 causes a non-foreseeable electronic behaviour of the later FinFET since the fin 290 (and thus the transistor) is not aligned with the crystal orientation of the underlying silicon substrate which, in most cases, causing drastically degraded electronic characteristics, as will be well-understood by an average-skilled person. These changes in electronic properties represent an exemplary design rule violation.
Another example for design rules is illustrated in FIG. 2B with two independent fin shapes 300 and 310 on a design hierarchy level n. On a design hierarchy level n+1, after assembling the two fin shapes 300, 310, as shown in the middle of FIG. 2B, the fins 300, 310 comprise a shape width 320 that falls below the minimum shape width thus representing another kind of design rule violation. The consequences of this design rule violation can be seen in the bottom part of FIG. 2B wherein, after lithographic processing of the fin 300, 310, a gap is generated between the original two fin shapes 300, 310 thus resulting in a broken connection between the two gate areas (200, 210 in FIG. 2A) causing failure of the FinFET.
A contiguous region as mentioned beforehand is formed in such a way that the fin structures within a region are designed and placed according to the mentioned design rules. Thus, the process of deriving the shape of the region is governed by the design rules. It initiates from the gate of each FET and spreads out orthogonally to both sides. Depending on the space between the FETs and the design rules, such a region can cover only one FET gate, but mostly covers a number of FETs.
Generally speaking, the above described fin-based chip design process includes first a design phase where the geometry i.e. shape (area, width, spacing, overlap etc.) of a fin structure is generated. Based on such a generated design, a lithography process is conducted that, at the end, provides an electronic structure (circuit layout) wherein only the circuit layout potentially reveals the above described and not desired electronic effects i.e. not wished interferences between adjacent fins or even failure of the whole circuit.
Further, as another requirement for the design of an underlying structure, an already existing design based on non-FinFET technology must not be changed particularly due to topology requirements and reuse of masks when performing a design transition introducing FinFET technology.
The above discussed technical requirements, in many cases, cause violation of at least one of the mentioned design rules when designing a fin-based or fin -shaped structure or when converting a not fin-based/shaped into a fin-based/shaped structure.
It is therefore desirable to provide a reliable method and device which enable a design-keeping transition of an existing non-fin design structure to a functionally identical structure based on FinFET technology.